CVE-2024-1543
published 2024-08-29CVE-2024-1543: The side-channel protected T-Table implementation in wolfSSL up to version 5.6.5 protects against a side-channel attacker with cache-line resolution. In a…
PriorityP424medium5.5CVSS 3.1
AVLACLPRLUINSUCHINAN
EPSS
0.18%
8.3th percentile
The side-channel protected T-Table implementation in wolfSSL up to version 5.6.5 protects against a side-channel attacker with cache-line resolution. In a controlled environment such as Intel SGX, an attacker can gain a per instruction sub-cache-line resolution allowing them to break the cache-line-level protection. For details on the attack refer to: https://doi.org/10.46586/tches.v2024.i1.457-500
Affected
9 ranges
| Vendor | Product | Version range | Fixed in |
|---|---|---|---|
| debian | wolfssl | < wolfssl 5.6.6-1.2 (forky) | wolfssl 5.6.6-1.2 (forky) |
| msrc | azure_linux_3.0_arm | — | — |
| msrc | azure_linux_3.0_x64 | — | — |
| msrc | cbl_mariner_2.0_arm | — | — |
| msrc | cbl_mariner_2.0_x64 | — | — |
| wolfssl | wolfssl | < 5.6.6 | 5.6.6 |
| wolfssl | wolfssl | <= 5.6.5 | — |
| wolfssl | wolfssl | >= 0 < 5.6.6-1.2 | 5.6.6-1.2 |
| wolfssl | wolfssl | >= 0 < 5.6.6-1.2 | 5.6.6-1.2 |
CVSS provenance
nvdv3.15.5MEDIUMCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N
osv5.5MEDIUM
vendor_debian4.1MEDIUM
vendor_msrc4.1MEDIUM
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Microsoft
AES T-Table sub-cache-line leakage
vendor_msrc·2024-08-13·CVSS 4.1
CVE-2024-1543 [MEDIUM] CWE-208 AES T-Table sub-cache-line leakage
AES T-Table sub-cache-line leakage
FAQ: Is Azure Linux the only Microsoft product that includes this open-source library and is therefore potentially affected by this vulnerability?
One of the main benefits to our customers who choose to use the Azure Linux distro is the commitment to keep it up to date with the most recent and most secure versions of the open source libraries with which the distro is composed. Microsoft is committed to transparency in this work which is why we began publishing CSAF/VEX in October 2025. See this blog post for more information. If impact to additional products is identified, we will update the CVE to reflect this.
Mariner: Mariner
wolfSSL: wolfSSL
Customer Action Required: Yes
Debian
CVE-2024-1543: wolfssl - The side-channel protected T-Table implementation in wolfSSL up to version 5.6.5...
vendor_debian·2024·CVSS 4.1
CVE-2024-1543 [MEDIUM] CVE-2024-1543: wolfssl - The side-channel protected T-Table implementation in wolfSSL up to version 5.6.5...
The side-channel protected T-Table implementation in wolfSSL up to version 5.6.5 protects against a side-channel attacker with cache-line resolution. In a controlled environment such as Intel SGX, an attacker can gain a per instruction sub-cache-line resolution allowing them to break the cache-line-level protection. For details on the attack refer to: https://doi.org/10.46586/tches.v2024.i1.457-500
Scope: local
bookworm: open
bullseye: open
forky: resolved (fixed in 5.6.6-1.2)
sid: resolved (fixed in 5.6.6-1.2)
trixie: resolved (fixed in 5.6.6-1.2)
GHSA
GHSA-w782-gjg9-cjx6: The side-channel protected T-Table implementation in wolfSSL up to version 5
ghsa_unreviewed·2024-08-30
CVE-2024-1543 [MEDIUM] CWE-203 GHSA-w782-gjg9-cjx6: The side-channel protected T-Table implementation in wolfSSL up to version 5
The side-channel protected T-Table implementation in wolfSSL up to version 5.6.5 protects against a side-channel attacker with cache-line resolution. In a controlled environment such as Intel SGX, an attacker can gain a per instruction sub-cache-line resolution allowing them to break the cache-line-level protection. For details on the attack refer to: https://doi.org/10.46586/tches.v2024.i1.457-500
OSV
CVE-2024-1543: The side-channel protected T-Table implementation in wolfSSL up to version 5
osv·2024-08-29·CVSS 5.5
CVE-2024-1543 [MEDIUM] CVE-2024-1543: The side-channel protected T-Table implementation in wolfSSL up to version 5
The side-channel protected T-Table implementation in wolfSSL up to version 5.6.5 protects against a side-channel attacker with cache-line resolution. In a controlled environment such as Intel SGX, an attacker can gain a per instruction sub-cache-line resolution allowing them to break the cache-line-level protection. For details on the attack refer to: https://doi.org/10.46586/tches.v2024.i1.457-500
No detection rules found.
No public exploits indexed.
No writeups or analysis indexed.
2024-08-29
Published