CVE-2024-24853
published 2024-08-14CVE-2024-24853: Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to…
PriorityP428high7.2CVSS 3.1
AVLACHPRHUIRSCCHIHAH
EPSS
0.23%
14.1th percentile
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Affected
1 ranges
| Vendor | Product | Version range | Fixed in |
|---|---|---|---|
| debian | intel-microcode | < intel-microcode 3.20240813.1~deb12u1 (bookworm) | intel-microcode 3.20240813.1~deb12u1 (bookworm) |
CVSS provenance
nvdv3.17.2HIGHCVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H
nvdv4.07.3HIGHCVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
osv7.3HIGH
vendor_ubuntu7.8HIGH
vendor_debian7.3HIGH
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OSV
intel-microcode vulnerabilities
osv·2024-08-20·CVSS 7.3
CVE-2023-42667 [HIGH] intel-microcode vulnerabilities
intel-microcode vulnerabilities
It was discovered that some Intel® Core™ Ultra Processors did not properly
isolate the stream cache. A local authenticated user could potentially use
this to escalate their privileges. (CVE-2023-42667)
It was discovered that some Intel® Processors did not properly isolate the
stream cache. A local authenticated user could potentially use this to
escalate their privileges. (CVE-2023-49141)
It was discovered that some Intel® Processors did not correctly transition
between the executive monitor and SMI transfer monitor (STM). A privileged
local attacker could use this to escalate their privileges.
(CVE-2024-24853)
It was discovered that some 3rd, 4th, and 5th Generation Intel® Xeon®
Processors failed to properly implement a protection mechanism. A local
att
GHSA
GHSA-vp6v-8xw7-8j3v: Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user
ghsa_unreviewed·2024-08-14
CVE-2024-24853 [HIGH] CWE-696 GHSA-vp6v-8xw7-8j3v: Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
OSV
CVE-2024-24853: Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user
osv·2024-08-14·CVSS 7.3
CVE-2024-24853 [HIGH] CVE-2024-24853: Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Ubuntu
Intel Microcode vulnerabilities
vendor_ubuntu·2024-08-20·CVSS 7.8
CVE-2023-42667 [HIGH] Intel Microcode vulnerabilities
Title: Intel Microcode vulnerabilities
Summary: Several security issues were fixed in Intel Microcode.
It was discovered that some Intel® Core™ Ultra Processors did not properly
isolate the stream cache. A local authenticated user could potentially use
this to escalate their privileges. (CVE-2023-42667)
It was discovered that some Intel® Processors did not properly isolate the
stream cache. A local authenticated user could potentially use this to
escalate their privileges. (CVE-2023-49141)
It was discovered that some Intel® Processors did not correctly transition
between the executive monitor and SMI transfer monitor (STM). A privileged
local attacker could use this to escalate their privileges.
(CVE-2024-24853)
It was discovered that some 3rd, 4th, and 5th Generation Intel® Xeon®
Pro
Debian
CVE-2024-24853: intel-microcode - Incorrect behavior order in transition between executive monitor and SMI transfe...
vendor_debian·2024·CVSS 7.3
CVE-2024-24853 [HIGH] CVE-2024-24853: intel-microcode - Incorrect behavior order in transition between executive monitor and SMI transfe...
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Scope: local
bookworm: resolved (fixed in 3.20240813.1~deb12u1)
bullseye: resolved (fixed in 3.20240813.1~deb11u1)
forky: resolved (fixed in 3.20240813.1)
sid: resolved (fixed in 3.20240813.1)
trixie: resolved (fixed in 3.20240813.1)
No detection rules found.
No public exploits indexed.
No writeups or analysis indexed.
2024-08-14
Published