cbcvebase.

Amd Epyc 7713 Firmware vulnerabilities

90 known vulnerabilities affecting amd/epyc_7713_firmware.

Total CVEs
90
CISA KEV
0
Public exploits
0
Exploited in wild
0
Severity breakdown
CRITICAL5HIGH36MEDIUM47LOW2

Vulnerabilities

Page 3 of 5
CVE-2023-20525P4MEDIUMCVSS 6.5fixed in milanpi_1.0.0.52023-01-11
CVE-2023-20525 [MEDIUM] CWE-20 CVE-2023-20525: Insufficient syscall input validation in the ASP Bootloader may allow a privileged attacker to read Insufficient syscall input validation in the ASP Bootloader may allow a privileged attacker to read memory outside the bounds of a mapped register potentially leading to a denial of service.
nvd
CVE-2023-20527P4MEDIUMCVSS 6.5fixed in milanpi_1.0.0.52023-01-11
CVE-2023-20527 [MEDIUM] CWE-20 CVE-2023-20527: Improper syscall input validation in the ASP Bootloader may allow a privileged attacker to read memo Improper syscall input validation in the ASP Bootloader may allow a privileged attacker to read memory out-of-bounds, potentially leading to a denial-of-service.
nvd
CVE-2021-46775P4MEDIUMCVSS 6.8vmilanpi_1.0.0.92023-05-09
CVE-2021-46775 [MEDIUM] CWE-20 CVE-2021-46775: Improper input validation in ABL may enable an attacker with physical access, to perform arbitrary m Improper input validation in ABL may enable an attacker with physical access, to perform arbitrary memory overwrites, potentially leading to a loss of integrity and code execution.
nvd
CVE-2021-26397P4HIGHCVSS 7.1fixed in milanpi_1.0.0.92023-05-09
CVE-2021-26397 [HIGH] CVE-2021-26397: Insufficient address validation, may allow an attacker with a compromised ABL and UApp to corrupt se Insufficient address validation, may allow an attacker with a compromised ABL and UApp to corrupt sensitive memory locations potentially resulting in a loss of integrity or availability.
nvd
CVE-2023-20569P4MEDIUMCVSS 4.7fixed in milanpi_1.0.0.c2023-08-08
CVE-2023-20569 [MEDIUM] CWE-203 CVE-2023-20569: A side channel vulnerability on some of the AMD CPUs may allow an attacker to influence the retur A side channel vulnerability on some of the AMD CPUs may allow an attacker to influence the return address prediction. This may result in speculative execution at an attacker-controlled address, potentially leading to information disclosure.
nvd
CVE-2021-26332P4HIGHCVSS 7.1fixed in milanpi-sp3_1.0.0.42022-05-10
CVE-2021-26332 [HIGH] CVE-2021-26332: Failure to verify SEV-ES TMR is not in MMIO space, SEV-ES FW could result in a potential loss of int Failure to verify SEV-ES TMR is not in MMIO space, SEV-ES FW could result in a potential loss of integrity or availability.
nvd
CVE-2020-12946P4HIGHCVSS 7.1fixed in milanpi-sp3_1.0.0.42021-11-16
CVE-2020-12946 [HIGH] CWE-20 CVE-2020-12946: Insufficient input validation in ASP firmware for discrete TPM commands could allow a potential loss Insufficient input validation in ASP firmware for discrete TPM commands could allow a potential loss of integrity and denial of service.
nvd
CVE-2023-31346P4MEDIUMCVSS 6.0fixed in milanpi_1.0.0.c2024-02-13
CVE-2023-31346 [MEDIUM] CWE-284 CVE-2023-31346: Failure to initialize memory in SEV Firmware may allow a privileged attacker to access stale data fr Failure to initialize memory in SEV Firmware may allow a privileged attacker to access stale data from other guests.
nvd
CVE-2022-23830P4MEDIUMCVSS 5.3fixed in milanpi_1.0.0.a2023-11-14
CVE-2022-23830 [MEDIUM] CVE-2022-23830: SMM configuration may not be immutable, as intended, when SNP is enabled resulting in a potential li SMM configuration may not be immutable, as intended, when SNP is enabled resulting in a potential limited loss of guest memory integrity.
nvd
CVE-2020-12954P4MEDIUMCVSS 5.5fixed in milanpi-sp3_1.0.0.42021-11-16
CVE-2020-12954 [MEDIUM] CWE-693 CVE-2020-12954: A side effect of an integrated chipset option may be able to be used by an attacker to bypass SPI RO A side effect of an integrated chipset option may be able to be used by an attacker to bypass SPI ROM protections, allowing unauthorized SPI ROM modification.
nvd
CVE-2021-26354P4MEDIUMCVSS 5.5fixed in milanpi_1.0.0.62023-05-09
CVE-2021-26354 [MEDIUM] CWE-120 CVE-2021-26354: Insufficient bounds checking in ASP may allow an attacker to issue a system call from a compromised Insufficient bounds checking in ASP may allow an attacker to issue a system call from a compromised ABL which may cause arbitrary memory values to be initialized to zero, potentially leading to a loss of integrity.
nvd
CVE-2023-31347P4MEDIUMCVSS 4.9fixed in milanpi_1.0.0.c2024-02-13
CVE-2023-31347 [MEDIUM] CWE-682 CVE-2023-31347: Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect TSC when Secure TSC is enabled potentially resulting in a loss of guest integrity.
nvd
CVE-2023-20584P4MEDIUMCVSS 6.0fixed in milanpi_1.0.0.b2024-08-13
CVE-2023-20584 [MEDIUM] CVE-2023-20584: IOMMU improperly handles certain special address ranges with invalid device table entries (DTEs), wh IOMMU improperly handles certain special address ranges with invalid device table entries (DTEs), which may allow an attacker with privileges and a compromised Hypervisor to induce DTE faults to bypass RMP checks in SEV-SNP, potentially leading to a loss of guest integrity.
nvd
CVE-2020-12966P4MEDIUMCVSS 5.5fixed in milanpi-sp3_1.0.0.52022-02-04
CVE-2020-12966 [MEDIUM] CWE-200 CVE-2020-12966: AMD EPYC™ Processors contain an information disclosure vulnerability in the Secure Encrypted Virtual AMD EPYC™ Processors contain an information disclosure vulnerability in the Secure Encrypted Virtualization with Encrypted State (SEV-ES) and Secure Encrypted Virtualization with Secure Nested Paging (SEV-SNP). A local authenticated attacker could potentially exploit this vulnerability leading to leaking guest data by the malicious hypervisor.
nvd
CVE-2021-26312P4MEDIUMCVSS 5.5fixed in milanpi-sp3_1.0.0.42021-11-16
CVE-2021-26312 [MEDIUM] CWE-665 CVE-2021-26312: Failure to flush the Translation Lookaside Buffer (TLB) of the I/O memory management unit (IOMMU) ma Failure to flush the Translation Lookaside Buffer (TLB) of the I/O memory management unit (IOMMU) may lead an IO device to write to memory it should not be able to access, resulting in a potential loss of integrity.
nvd
CVE-2021-26348P4MEDIUMCVSS 5.5fixed in milanpi-sp3_1.0.0.72022-05-11
CVE-2021-26348 [MEDIUM] CVE-2021-26348: Failure to flush the Translation Lookaside Buffer (TLB) of the I/O memory management unit (IOMMU) ma Failure to flush the Translation Lookaside Buffer (TLB) of the I/O memory management unit (IOMMU) may lead an IO device to write to memory it should not be able to access, resulting in a potential loss of integrity.
nvd
CVE-2021-26371P4MEDIUMCVSS 5.5fixed in milanpi_1.0.0.62023-05-09
CVE-2021-26371 [MEDIUM] CVE-2021-26371: A compromised or malicious ABL or UApp could send a SHA256 system call to the bootloader, which may A compromised or malicious ABL or UApp could send a SHA256 system call to the bootloader, which may result in exposure of ASP memory to userspace, potentially leading to information disclosure.
nvd
CVE-2023-20532P4MEDIUMCVSS 5.3fixed in milanpi_1.0.0.52023-01-11
CVE-2023-20532 [MEDIUM] CWE-20 CVE-2023-20532: Insufficient input validation in the SMU may allow an attacker to improperly lock resources, potenti Insufficient input validation in the SMU may allow an attacker to improperly lock resources, potentially resulting in a denial of service.
nvd
CVE-2023-31355P4MEDIUMCVSS 6.0fixed in milanpi_1.0.0.d2024-08-05
CVE-2023-31355 [MEDIUM] CWE-119 CVE-2023-31355: Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to overw Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to overwrite a guest's UMC seed potentially allowing reading of memory from a decommissioned guest.
nvd
CVE-2021-26337P4MEDIUMCVSS 5.5fixed in milanpi-sp3_1.0.0.42021-11-16
CVE-2021-26337 [MEDIUM] CVE-2021-26337: Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from i Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.
nvd